One of the best lab classes in UCD. Verilog is not intuitive and has mountains of documentation. Just search how to do things. Akella gives many many examples of code in lecture. So you should scarcely have any problems with the labs.

Verilog modelling of combinational and sequential circuits. Timing analysis. Brief coverage of CMOS implementation. Very useful stuff.

He cares a lot about his students and their ability to learn. He is happy to see you outside of class, and he extends his office hours too.

Make sure you do computer architecture (EEC 170) before this class, because it will help you build a nice project.

Computer performance analysis, Assembly basics, building a CPU, and memory hierarchy. Loved the content of the courses - very interesting. Walking through the structure of a CPU, then working through ways to improve performance and throughput were the highlight for me.

Understanding the basic of a computer architecture - CPU structure, Memory Hierarchy, basic Assembly. RISC-V architecture was used.

Lectures were engaging, but the examples we go through and the homework assigned do not adequately prepare you for the quizzes and exams. Generous curve at the end of the course though.

Attend lectures and ask questions. Do the homework problems yourself before looking up solutions. For every topic discussed in lecture, find an example problem for to solve.