Very useful content, teaches the fundamentals of VHDL, digital system design, and assembly that some future courses build up on, and course material is interesting. However, be prepared to spend lots of time on labs. There are weekly labs that are marked in demo sessions with TAs, and each one can take 10-20 hours of your time to do well enough to get full marks. The course also has several defaulting policies, for example you MUST pass the final to pass the course. Additionally, after some of the labs, they will have an LPT to test proficiency on lab content, and you also need to achieve a certain threshold on those to pass the course. You'll be spending so much time on the labs that you likely won't have much time to study for exams, so it can be tough to get a high grade on them. Howeve...read more

He is a good lecturer, but will make the lives of students very difficult with his draconian defaulting policies and difficult labs.

- Have a good lab partner, and set consistent meeting times to complete labs each week - Go to lab office hours as often as you can. TAs are very helpful - Read the textbook to understand course content. It is well written

Very interesting course, and the labs are challenging but rewarding, assuming you can keep up. All the exams are brutal but there are opportunities for part marks and they're scaled. Lab exams and labs are largely autograded, and punish mistakes hard, producing a very bimodal 100 or 0 mark distribution. The textbooks are good if prone to misprints, and are both on libgen. Course policies from hell: a draconian anti collaboration policy bans most all discussion of labs, which interferes with those who fall behind catching up. A newly introduced rule this year meant anyone who failed too many of their lab exams would fail the course. The marking on these was automated and excessively harsh: on the last one, there was a function IGXHY that if you spelled it wrong, you'd fail the exam and...read more

Do not fall behind in labs. A good lab partner will help immensely in this course. Test exhaustively. Write a lot of (automated!) test code. Our final Verilog lab had 1.5x as much test code as hardware description language, and did not lose marks. Try to write the best and most understandable Verilog you can, and independently read about best practices and features you can use; you're going to be writing hundreds to over a thousand lines of it, and spending a lot of time in the debugger, so the easier it is to read both test code and hardware description, the better. (the task feature was invaluable in making our tests more readable) Speaking of the debugger, *learn what ModelSim can do for you* (e.g. breakpoints, traceback, $stop, etc for automated tests). You will be spending dozens of...read more

The hardest course I've ever took in my entire life.

Very useful course, you'll probably learn more in this course than most people in their entire life about computers, it should really be a 10 credit course. BE SURE NOT TO FALL BEHIND otherwise you will pay a high price for it.

Study far in advance for exams